Programmer's Model:

The 68000 microprocessor will execute instructions (run programs) in either User or Supervisor mode. The User Mode (default) provides the execution environment for the majority of application programs. Supervisor Mode allows some additional instructions (i.e.; STOP RESET) and privileges and is intended for use by the operating system.

As shown below, the 68000 is made up of eight 32 bit data registers (D0-D7), eight 32 bit address registers (A0-A7), a 32 bit user and a 32 bit supervisor stack pointer (USP & SSP), a 32 bit program counter (PC) and a Status Register which contains the flags for the Condition Code Register (CCR)

	Figure 1: Programmer's Model

The data registers may be accessed as 8 bit (Byte Size Data), 16 bit (Word Size Data) or 32 bit (Longword Size Data) Registers. The address registers (A0-A7), PC, USP & SSP may be accessed as 16 bit or 32 bit registers only. The address registers and the USP may be used as Stack Pointers and as Base Address Registers (used in Register Indirect Addressing Mode - more later). All 8 data registers and all 8 address registers may be used as index registers (more later). The Status Register/Condition Code Register is layed out as follows:

	Figure 2: Status/Condition Code Register

The upper 8 bits of this register (Status Register section) is unavailable to the programmer unless the processor is in the Supervisor State. The T bit (Trace) enables the 68000 to single step through a program. This can be used to assist the programmer in debugging a new program. The S bit (Supervisor State) controls the operating mode of the processor (S=0 for User Mode, S=1 for Supervisor Mode). There are special instructions that allow the programmer to manipulate this bit. Bits 8-10 are the Interrupt Masks. These bits are used to determine what level of interrupt the 68000 will respond. The 68000 will only mask interrupt levels that are lower than the binary value of these bits. Level 7 (111) is the highest number that can be placed in these bits. This means that all levels below seven would be masked, but level 7 would be acknowledged. This fact makes level 7 equivalent to a Non-Maskable Interrupt.

The lower 8 bits of this register (Condition Code Register section) is available to the programmer in either state. The following is a brief description of each bit:

	Z bit	The Zero bit will be set (Z=1) anytime the result of an instruction is 0.
	N bit	The Negative bit will be set (N=1) anytime the Most Significant Bit (MSb)
		of a result is equal to 1 (indicating a negative number when using 2's compliment numbers).
	C bit	The Carry bit is set (C=1) whenever there is a carry out of the MSb after the
		completion of an instruction.
	V bit	The Overflow bit is set (V=1) whenever there is a 2's Compliment Overflow
		from a result.
	X bit	The Extend bit (X) is usually either unaffected or set the same as the C bit.

The CCR (Condition Code Register) will be looked at more closely with the Instruction Set. It is important at this point to know that these bits are set (1) or reset (0) by the result of an instruction and that the programmer uses the state of these bits to make decisions in his/her program through the use of Branch instructions.

Functional Description:

The 68000 is referred to as a 16/32 bit microprocessor. It has a 16 bit data bus, but 32 bit internal registers. This means that it can transfer 16 bits per Read or Write cycle, but can work with 32 bit numbers.

The 68000 physically has a 23 bit address bus (A1-A23). A0 is encoded by two control signals: Lower Data Strobe (/LDS) and the Upper Data Strobe (/UDS). Therefore, the 68000 has, in effect, a 24 bit address bus, enabling it to address 16MB of memory (2 24 bytes).

The 68000 has two modes for data transfer: Asynchronous & Synchronous

Asynchronous mode is used with 68xxx peripheral and memory devices through a control signal known as Data Transfer Acknowledge (/DTACK) Synchronous mode is used with older 68xx peripherals through the use of three control signals: E, Valid Peripheral Address (/VPA), and Valid Memory Address (/VMA).

The 68000 is contained in a 64 pin Dual In-line Package (DIP) and uses a single 5v supply voltage (+5v connected to pins 49 and 14, Ground connected to pins 53 and 16). There are multiple versions of the 68000 for different clock frequencies ranging from 4MHz to 12.5MHz.

Data Organization:

68000 instructions can direct the processor to work on five data types:

		bit
		Binary Coded Decimal (BCD - 4 bits)
		Byte (8 bits)
		Word (16 bits)
		Longword (32 bits)

Instructions that affect only a byte of data, will affect only the lowest order bits in a register (b0-b7). Instructions that affect only a byte of word, will affect only the lowest order bits in that register (b0-b15). Longword instructions will affect the complete register. Although the 68000 has a 16 bit data bus, the programmer can choose to store or retrieve a byte of data from memory. The 68000 handles this request through the use of the data strobes. If an even address is referenced when transferring a byte of data, /UDS becomes active, and data is transferred along D8-D15 of the Data Bus. If an odd address is referenced when transferring a byte of data, /LDS becomes active, and data is transferred along D0-D7 of the Data Bus. If a word or longword of data is being transferred, both /UDS and /LDS become active and the data must be stored at an even address. The 68000 will not allow word or longword data transfers to odd addresses. If a programmer inadvertently attempts to do so, the 68000 will generate an exception (a software error) and halt. This concept is summarized in the term: Word Boundary. Word Boundaries exist at every even address. See Odd Address Error Animation When storing words or longwords in memory, the Most Significant Byte (MSB) is stored at the address specified, the next lowest byte in the next address, and so on until the data is stored

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Copyright Stephen J Kuyath, UNCC
last modified: January 3, 2007