ECGR 4132/5132 Analog Integrated Circuit Design

This course prepares students at the senior/master's level for transistor-level, analog CMOS integrated circuit design by developing an understanding of MOS modeling and transistor-level circuit analysis. Application of modeling and analysis is applied to MOS current mirrors, operational amplifiers, feedback amplifiers, and other analog circuits. Emphasis is placed on hand design with SPICE computer simulation used for verification. Course makes use of professor's notes, motivated by industry analog and mixed-signal CMOS design experience. Course topics include:

• Example industry, mixed-signal CMOS chips
• Overview of CMOS fabrication
• MOS I-V, small-signal, and capacitance modeling (strong inversion)
• MOS body effect, channel-length modulation, and other effects
• MOS sizing for optimum analog design (strong inversion)
• Bias analysis and design of CMOS circuits
• Small signal analysis and design of CMOS circuits
• SPICE simulation of 0.5-μm CMOS circuits using the recent EKV MOS model
• CMOS common-source, grounded-gate, and source-follower stages
• CMOS current mirrors and simple, low-voltage, and regulated cascodes
• CMOS reference circuits
• Feedback amplifier analysis and design
• CMOS differential amplifiers
• CMOS operational amplifiers
• CMOS single-stage, gain-enhanced, dominant-pole operational amplifiers

PSPICE simulation with text based entry

• Model files:
  Download the model parameter file that is necessary for the MOSFET simulation.
  The one we'll be working with mostly is the EKV V2.6 model paramater file. More about the EKV parameters can be read in the EKV2.6 report.
  
  We might also work with the BSIM3 parameters. Here is a parameter file from MOSIS for the 0.5-μm AMI_C5N process: AMI_C5N_TOBI.
  
  
• Simulation file:
  To simulate your circuit you need to create a .cir file containing all your commands. A simple explanation of a example circuit mirror circuit describes the steps. Copy the .cir file to simulate the example and compare your results with the outfile. Text-based SPICE entry is used to ensure areas and perimeters of MOSFET drain and source diffusions are properly modeled for correct capacitances.