ECGR 6xxx/8xxx Advanced Analog Integrated Circuit Design

This course prepares students at the master’s/Ph.D. level for advanced transistor-level, analog CMOS integrated circuit design by presenting a design methodology developed by the professor for design over all regions of MOS operation, weak through strong inversion, for all available channel lengths. Course material is taken from conference tutorials/short courses given by the professor and permits optimized tradeoffs in bandwidth, dc gain, dc matching, white noise, flicker noise, and other circuit performances. Advanced concepts such as MOS noise, dc mismatch, and short-channel effects are presented and applied in the analysis and design of modern operational amplifier and other analog circuits. The EKV MOS model is utilized to consider dc mismatch and noise. Course topics include:

• Modeling the MOS transistor over weak, moderate, and strong inversion
• MOS inversion coefficient (IC) for weak (IC < 0.1), moderate (0.1 < IC < 10), and strong inversion (IC > 10)
• MOS V_GS, V_DSAT, g_m, g_mb, g_ds, capacitance, f_T, noise, etc., versus IC and channel length (L)
• MOS velocity saturation effects at high inversion, short L
• MOS local area dc mismatch
• MOS flicker noise
• MOS white noise
• MOS drain current, IC, and L for optimum bandwidth, dc gain, dc matching, noise, saturation voltage, etc.
• Noise analysis of MOS circuit
• SPICE noise and dc mismatch analysis of 0.5-μm CMOS circuits using the EKV MOS model
• Design of advanced CMOS current mirrors, including low-voltage circuits
• Design of CMOS transconductors and other analog building blocks
• Design of low-noise CMOS preamplifiers
• Design of advanced CMOS operational amplifiers

PSpice Simulation:
Here is a model parameter file for a generic 0.5 μm CMOS process. The file contains the given parameter values from Razavi's book "Design of Analog CMOS Integrated Circuits", from Table 2.1 on page 37. The parameter file uses the EKV model.