BEFORE DOWNLOADING THE DESIGN SPREADSHEETS, PLEASE DETERMINE THE SPREADSHEETS YOU WOULD LIKE.
Description of Analog CMOS Design, Tradeoffs and Optimization Design Spreadsheets
The tables below describe the design spreadsheets. Book references are to David M. Binkley, Tradeoffs and Optimization in Analog CMOS Design, John Wiley and Sons, Ltd, 2008, ISBN: 978-0-470-03136-0, www.wiley.com/go/binkley_tradeoffs. User inputs and performance calculations for the spreadsheets are described in detail in the book Appendix.
Table 1. Device tradeoffs and optimization for nMOS devices in a typical 0.18‑μm CMOS process. The spreadsheets described below illustrate the tradeoffs and optimization of individual MOS devices or related devices like differential pairs and current mirrors. Each of these spreadsheets contains MOSFETs, Process, and License, Notes sheets. The MOSFETs sheet evaluates MOS device performance for user selections of MOS drain current, inversion coefficient, and channel length. Only one spreadsheet needs to be downloaded to evaluate MOS device performance.
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Design spreadsheet description and filename (each file is approximately 240 kB) |
Book references |
MOS design choices |
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IC |
L (μm) |
ID (μA) |
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Performance versus the inversion coefficient (IC)
MOSDesign,IC0.1-30,L1um,ID100uA,nMOS,0.18um.xls |
Sections 4.4, 4.4.1, 4.4.5; Figure 4.20 |
0.1- 30 |
1 |
100 |
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Performance versus the channel length (L)
MOSDesign,IC10,L4-0.18um,ID100uA,nMOS,0.18um.xls |
Sections 4.4, 4.4.2, 4.4.5; Figure 4.21 |
10 |
4-0.18 |
100 |
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Performance versus the drain current (ID)
MOSDesign,IC1,L1um,ID1-100uA,nMOS,0.18um.xls |
Sections 4.4, 4.4.3, 4.4.5; Figure 4.22 |
1 |
1 |
1-100 |
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DC, balanced, and AC optimization at millipower operation (ID = 100 μA)
MOSDesign,DC,Balanced,AC,ID100uA,nMOS,0.18um.xls |
Sections 4.4, 4.4.4, 4.4.5; Figure 4.23 |
1, 3, 10 |
1, 0.48, 0.18 |
100 |
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DC, balanced, and AC optimization at micropower operation (ID = 1 μA)
MOSDesign,DC,Balanced,AC,ID1uA,nMOS,0.18um.xls |
Sections 4.4, 4.4.4, 4.4.5; Figure 4.24 |
0.3, 1, 3 |
5.4, 2.6, 0.85 |
1 |
Table 2. DC, balanced, and AC optimization of simple, 0.5-μm CMOS operational transconductance amplifiers (OTAs). The spreadsheet described below illustrates the optimization of simple OTAs in a typical 0.5‑μm CMOS process. In a given OTA version, MOS inversion coefficients, channel lengths, and drain currents are equal. This does not minimize noise or mismatch performance, but provides simple design examples typical of general purpose designs. Inversion coefficients and channel lengths are varied across the OTA versions to give DC, balanced, and AC optimizations. Drain currents are held constant across the OTA versions to permit optimizations at equal power consumption. The spreadsheet contains MOSFETs, Circuit Analysis, Process, and License, Notes sheets. The MOSFETs sheet evaluates MOS device performance for user selections of MOS drain current, inversion coefficient, and channel length and maps this into complete OTA circuit performance in the Circuit Analysis sheet. The Circuit Analysis sheet contains circuit analysis specific to the OTA circuit.
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Design spreadsheet description and filename (the file is approximately 255 kB) |
Book references |
MOS design choices |
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IC |
L (μm) |
ID (μA) |
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DC, balanced, and AC optimization of simple, 0.5-μm CMOS OTAs
MOSDesign,Three,Simple,0.5um,CMOSOTAs |
Sections 5.1-5.4, 5.6; Figures 5.3, 5.4 |
1, 3, 10 |
4, 1.2, 0.85 |
50 |
Table 3. DC, balanced, and AC optimization of cascoded, 0.18-μm CMOS operational transconductance amplifiers (OTAs). The spreadsheet described below illustrates the optimization of cascoded OTAs in a typical 0.18‑μm CMOS process. In order to minimize thermal noise, input devices are operated at low inversion coefficients in moderate inversion for high gm/ID, while critical non-input devices are operated at high inversion coefficients in strong inversion for low gm/ID. Additionally, some critical non-input devices are operated at lower drain currents than input devices. MOS inversion coefficients and drain currents are different for different devices, with these remaining constant across the OTA versions. Channel lengths are varied across the OTA versions to give DC, balanced, and AC optimizations. Drain currents are held constant across the OTA versions to permit optimizations at equal power consumption. The spreadsheet contains MOSFETs, Circuit Analysis, Process, and License, Notes sheets. The MOSFETs sheet evaluates MOS device performance for user selections of MOS drain current, inversion coefficient, and channel length and maps this into complete OTA circuit performance in the Circuit Analysis sheet. The Circuit Analysis sheet contains circuit analysis specific to the OTA circuit.
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Design spreadsheet description and filename (the file is approximately 255 kB) |
Book references |
MOS design choices |
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IC |
L (μm) |
ID (μA) |
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DC, balanced, and AC optimization of cascoded, 0.18-μm CMOS OTAs
MOSDesign,Three,Cascoded,0.18um,CMOSOTAs |
Sections 5.1-5.3, 5.5, 5.6; Figures 5.11-5.14 |
0.8 (in); 16 (out) |
2, 0.48, 0.18 |
100 (in); 50, 150 (out) |
Table 4. Thermal and flicker noise optimization of micropower, low-noise, 0.35-μm CMOS preamplifiers. The spreadsheet described below illustrates the optimization of micropower, low-noise preamplifiers in a 0.35‑μm, partially depleted, SOI CMOS process, which has similar thermal and flicker noise as a bulk process. In order to minimize thermal noise, input devices are operated at low inversion coefficients in moderate inversion for high gm/ID, while critical non-input devices are operated at high inversion coefficients near or in strong inversion for low gm/ID. Additionally, some critical non-input devices utilize resistive source degeneration, using deep-ohmic MOS devices, to minimize their thermal and flicker noise contributions. Channel lengths are increased for critical non-input devices above that of the input devices to ensure sufficient gate area. This ensures input devices dominate flicker noise, as well as thermal noise. Both differential and single-ended input preamplifiers are considered, each operating at a core current consumption of 2 μA. The spreadsheet contains MOSFETs, Circuit Analysis, Process, and License, Notes sheets. The MOSFETs sheet evaluates MOS device performance for user selections of MOS drain current, inversion coefficient, and channel length and maps this into complete preamplifier circuit performance in the Circuit Analysis sheet. The Circuit Analysis sheet contains circuit analysis specific to the preamplifier circuits.
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Design spreadsheet description and filename (the file is approximately 246 kB) |
Book references |
MOS design choices |
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IC |
L (μm) |
ID (μA) |
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Thermal and flicker noise optimization of micropower, low-noise, 0.35-μm CMOS preamplifiers
MOSDesign,Two,Micropower,LowNoise,0.35um,CMOSPreamps.xls |
Sections 6.7-6.10; Figures 6.9-6.11, 6.14 |
0.95, 1.9 (in); 8.4, 38 (out) |
20 and above |
0.5, 1 |
BEFORE DOWNLOADING DESIGN SPREADSHEETS, PLEASE REVIEW AND PRINT THE FREEWARE LICENSE AGREEMENT.
(This FREEWARE LICENSE AGREEMENT also appears on the License, Notes sheets in the Analog CMOS Design, Tradeoffs and Optimization design spreadsheets.)
FREEWARE LICENSE AGREEMENT, VERSION 2008-0
for Analog CMOS Design, Tradeoffs and Optimization design spreadsheets
Copyright © 2000-2008 David M. Binkley
ATTENTION. READ CAREFULLY:
By downloading, copying, or using the Analog CMOS Design, Tradeoffs and Optimization design spreadsheets or downloading, copying, using, or distributing their derivatives (pursuant to Section 2.2, you may only distribute derivatives), you agree to the following FREEWARE LICENSE AGREEMENT (“Agreement”).
1. LICENSE. David M. Binkley (“author”) hereby grants licensee (“you”) a non-exclusive license to use the Analog CMOS Design, Tradeoffs and Optimization design spreadsheets (“the spreadsheets”), copyrighted by the author, and their derivatives. “Derivatives” collectively refer to changes to the operation of the MOSFETs, Circuit Analysis (where present), Process, or License, Notes sheets in the spreadsheets, excluding changes in user inputs or the addition or deletion of spreadsheet columns for different MOSFETs or MOSFET models. “Derivatives” also collectively refer to changes to the spreadsheet software code (“software code”) or the addition of different sheets to the spreadsheets. Under the terms of this license, you may:
1.1. Use the spreadsheets or derivatives on any computer in your possession.
1.2. Make copies of the spreadsheets or derivatives for your own use.
2. LIMITATIONS ON LICENSE. The license granted in Section 1 is subject to the following restrictions:
2.1. The spreadsheets or derivatives may not be offered for sale or embedded within a product offered for sale.
2.2. The spreadsheets may not be distributed to others, but can be separately downloaded by others from the author (the intention here is to track the use of the spreadsheets). Derivatives may be distributed to others, although the author encourages spreadsheet downloads from the author as a way to track the use of the spreadsheets and derivatives.
2.3. The copyright notices located at the top of MOSFETs, Circuit Analysis (where present), Process, and License, Notes sheets and at the top of the software code must be preserved in the spreadsheets. For spreadsheet derivatives, a prominent notice, “Derived from the Analog CMOS Design, Tradeoffs and Optimization design spreadsheet, Copyright © 2000-2008 David M. Binkley”, must appear at the top of all derivative sheets and at the top of derivative software code.
2.4. The FREEWARE LICENSE AGREEMENT located on the License, Notes sheet must be preserved in the spreadsheets and derivatives.
2.5. When the spreadsheets are included in publications or presentations, credit should be given to the author. When derivatives are included in publications or presentations, credit should be given to the author for the original spreadsheets used for the derivatives.
3. NOT FOR ACTUAL DESIGN, NO WARRANTY, LIMITATION OF LIABILITY, AND INDEMNIFICATION.
3.1. The spreadsheets and derivatives are intended for design guidance only, not for actual design, and do not correspond to any particular CMOS fabrication process. You must independently validate designs using MOS models and parameters appropriate for the actual fabrication process used.
3.2. Use of the spreadsheets or derivatives expressly indicates the assumption of risk that these should only be used for design guidance and should not be used for actual design or the validation of actual design. Additionally, use of the spreadsheets or derivatives expressly indicates acknowledgement of responsibility for independently validating designs using MOS models and parameters appropriate for the actual fabrication process used.
3.3. The spreadsheets and derivatives are provided without express or implied warranties that the information is accurate or reliable, and there are no warranties as to fitness for any particular purpose. The author accepts no responsibility or liability for loss or damage occasioned to any person or property through using the spreadsheets or derivatives, or acting or refraining from acting as a result of such use. The author expressly disclaims all implied warranties, including merchantability of fitness for any particular purpose. There will be no duty on the author to correct any errors or defects in the spreadsheets or derivatives.
3.4. You and those you distribute derivatives to (pursuant to Section 2.2, you may only distribute derivatives) shall defend, indemnify, and hold harmless the author from any claim, demand, liability, damage award, suit, judgment, or other legal action arising out of your use, distribution, modification, or duplication of the spreadsheets or derivatives.
4. TERMINATION. The license granted hereunder is effective until terminated by the author. You may terminate this license at any time by destroying all copies of the spreadsheets and derivatives. This license will terminate automatically if you do not comply with the limitations described above. On termination of the license, you must destroy all copies of the spreadsheets and derivatives.
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