ECGR 6090/8090--CMOS DATA CONVERTERS

Course Handout

Project Assignment
Cyclic ADC, 1.5 bit , 1 stage  
   
Steve Tucker 10-bit, 500 ksps, Vdd=3V
Robert Crawford 10-bit, 200 ksps, Vdd=5V
Matt Davis 8-bit, 400 ksps, Vdd=5V
Chris Wichman 8-bit, 200 ksps, Vdd=3V
   
   
Delta-Sigma ADC, 2nd order, 1-bit quantizer  
   
Alan Calder 14-bit, fin=20 KHz, Vdd=5V
Zhan Chen 12-bit,  fin=20 KHz, Vdd=3V
Don Leiu 12-bit,  fin=40 KHz, Vdd=5V
   

Useful Links

Design Review: Pipelined ADC, A. Abo, UC Berkeley.

ADC Class Design Projects: U. of Michigan

Project Schedule
March 23rd Design Review 1: System Modeling and determination of circuit specifications
March 25th Design Review 1 contd.
March 30th Design Review 2: OTA and Comparator circuit review
April 1st Design Review 2 contd.
April 13th Journal Paper Review
April 15th Journal Paper Review contd.
April 20th Design Review 3: ADC circuit review
April 22nd Design Review 3 contd.
May 4th Design Review 4: post layout simulation
May 6th Design Review 4 contd.
May 31st Fabrication Deadline

Design Review requirements

Email your presentations a day before the design review. The order of presentation will be Steve, Robert, Matt and Chris (Day1) Alan, Zhan and Don (Day2).

Design Review 1: 1) Block level schematic of ADC 2) Tabulated circuit specifications 3) Derivation of circuit specifications (OTA, Capacitor, Switches, Comparators and Clock. 4) Relevant plots.

SteveTucker_CyclicADC

Design Review 2: 1) OTA specifications 2) OTA node voltages and sizing of transistors 3) Gain and phase response 4) Common mode response with zero differential input 5) Output with a 10uV differential step input.

 

Journal Paper Review List

Design Homework (Due March 2):

Design a fully differential folded cascode OTA in 0.5μm CMOS with the specifications given below. The power consumption is to be minimized and the common-mode feedback implemented using switched capacitor techniques. Assume a clocking frequency of 10MHz.

VDD = 5V, DC gain = 70dB, CL = 1pF, Unity Gain bandwidth = 100 MHz, Phase Margin = 70o ,Output swing = 2Vp-p, Slew rate = 100V/μs. 

Assignment 1

Assignment 2
Assignment 3 Assignment 4
Assignment 5 Assignment 6
Assignment 7 Assignment 8
Assignment 9 Assignment 10
Assignment11  

 

Announcements/Postings:-

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Posted 1/15: Assignment 2: Use the cell switch_cap_integ instead of sah_ideal from Library ahdlLib

 
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Posted 1/18: In the ocnPrint command, use 'numberNotation' instead of 'numbernotation'
 
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Posted 1/20: For device models, first "untar" the mosis_ami0.5_corners.tar file in ~/cadence/NCSU using the command "tar -xvf mosis_ami0.5_corners.tar". To include the models for simulation, from the Analog Design Enviroment (that's where you run your simulations from), under "setup"-> "Model Libraries" include the path to the files ntt.typ and ptt.typ in the directory "mosis_ami0.5_corners". You only need to do this once if you save the simulation state before exiting Cadence. You can load the state next time you use Cadence.

 
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Posted 3/18: Change in course grading: Exam: 20%,  Design Review 1: 10%, Design Review 2: 10%, Design Review 3: 20%, Design Review 4: 10%, Final Report: 10% and Journal paper review: 20%.

 

  
 

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