Hardware
Acceleration using FPGAs
Catalog
Listing "Introduction to VHDL"(ECGR
4146/5146 )
Spring 2008
A
Design Flow is similar to a Cascading Waterfall
Lecture Timings 9:30am - 10:45am Monday,Wednesday Room: Woodward 120
TA
for class : Siddharth Datta (skdatta@uncc.edu)
TA
office : WH 237/238
TA
office hours : Fridays 1pm - 4pm
Instructor office hours : Monday 2 pm - 3:30 pm @
Woodward 235B/235A/254
Instructor Dr. Arindam Mukherjee / Dr. Arun
Ravindran
Course
Description
This
course is designed for junior/senior undergraduate students with a
background
in digital logic design and VHDL. The class meets twice a week with
alternating
lectures and laboratories. The lectures and laboratory sessions seeks
to impart
students the ability for FPGA based reconfigurable hardware
implementation of
computationally intensive algorithms from diverse areas such as
bioinformatics,
scientific computing and image processing. No background knowledge of
these
topics is required. Students are required to complete a design project
involving implementation of a real world computational application on
FPGAs.
CAD tools including Xilinx ISE design flow and Modelsim are used
extensively
throughout the course.
Course Objectives
Ability
to describe digital logic in VHDL.
Familiarity
with FPGA design flow including interfacing issues.
Exposure
to computing algorithms from diverse application areas.
Ability
to map computationally intensive algorithms to FPGAs.
Successful
project execution and presentation of results working in a team.
Prerequisites
ECGR 3181 Advanced Digital
Logic Systems.
Textbook
P.J.
Ashenden, The Designer’s Guide to VHDL, Morgan Kaufmann, 1996.
Grading
Midterm –
20%, Laboratory
– 30 %, Final
Project – 40%, Class Participation – 10 %
Course Topics (Subject to
change)
- Review of Finite
State
Machines
- Overview of VHDL
– Structure and Syntax
- Overview of VHDL
– Modeling
- Overview of VHDL
- Synthesis
- FPGA Design Flow
- Interfacing FPGA
based hardware accelerators to computers
- Design Case
Study: Design of a multiplier
- Design Case
Study: Accelerating the Smith Waterman algorithm (bioinformatics)
- Design Case
Study: Accelerating Jacobi’s matrix diagonalization algorithm
(scientific computing)
- Design Case
Study: Accelerating Prewitt edge detection algorithm (image processing)
- Projects
Lecture
Notes
Instructions on using ModelSim
source
/afs/uncc.edu/coe/unix/opt/mgc/cshrc.en2002
vsim
ModelSim Manual
Xilinx ISE Tutorial
Xilinx
Virtex-5 FPGAs